intellectual property core (IP core)
What is an intellectual property core (IP core)?
An intellectual property core (IP core) is a functional block of logic or data used to make a field-programmable gate array (FPGA) or application-specific integrated circuit for a product.
Commonly used in semiconductors, an IP core is a reusable unit of logic or integrated circuit (IC) layout design. It is the IP of one party and may be licensed by others for use in their own ICs and semiconductors.
IP cores explained
In modern IC designs, an increasing number of system functionalities are integrated into single chips. This type of design is known as a system-on-a-chip (SOC) design. Most SOC chips incorporate a standard microprocessor and standardized functionalities, accommodating design reuse across multiple ICs by multiple vendors on a licensing basis. In these systems, pre-designed IP cores play a key role.
An IP core is usually a standalone module that's part of a larger device or system, such as a processor or other complex IC. It incorporates electronic circuitry whose use is licensed by the original designer to other companies. The designer would test the IP core before licensing it to others.
Most IP cores are developed using hardware description languages (HDLs), like VHSIC HDL, Verilog or SystemVerilog. An HDL is analogous to a computer software program. A high-level specification language, like C, can also be used to develop an IP core.
Examples of IP cores
The following are common examples of IP cores:
- universal asynchronous receiver/transmitter
- central processing unit (CPU)
- Ethernet controllers
- Peripheral Component Interconnect interfaces
- microcontrollers
- standard bus interfaces
Memory controllers and 3D graphics units are also types of IP cores. An entire processor can be an IP core.
Benefits of IP cores
IP cores support design reuse. Electronics engineers and designers use them to implement components of unique logic and ICs faster than they could otherwise. Since they accommodate repeated reuse of previously designed components, they contribute to the electronic design automation industry.
A company that purchases an IP core license usually receives everything that's required to design, test and implement it in its own product. They may also receive the following:
- logic and test patterns
- signal specifications
- associated software
- design notes and other documentation
- list of known bugs or limitations
For best results, an IP core should be entirely portable, meaning it should be possible to easily insert it into any vendor technology or design methodology to enable repeated reuse.
Types of IP cores
There are three main categories of IP cores.
1. Hard IP core
A hard IP core is a physical manifestation of the IP's design. The IP owner usually offers the hard IP core as a layout design mapped to a process technology. Another vendor or design house can license the IP and use the design in the final layout of its own chip.
A hard core is not portable or flexible, unlike the other two types of cores. The core designer must configure the location and interface connectivity with other modules, clocks and resets. It has a fixed location in the FPGA and cannot be ported to other FPGAs or customized for different process technologies.
The advantage of the hard IP core is that it reduces the need for code maintenance. It also minimizes timing violations, fosters high performance and functionality, and provides a low-cost IP core option since it is included in the FPGA.
The drawback of the hard IP core is its lack of portability and that it comes with predefined constraints. This makes it best used for plug-and-play applications. When provided as mixed-signal and analog designs, hard IP cores are also suitable for applications requiring specific signal timing or physical layouts.
2. Firm IP core
A firm IP core, or semihard IP core, can be configured and modified for different applications. Compared to a hard core, it provides greater flexibility to place the module in the FPGA and interconnect it with other modules. It also minimizes the need for user-programmable configurations. Once the firm component is instantiated at the top level, it can be moved around within the FPGA to satisfy performance and timing requirements.
The functionality and performance of a firm IP core are measurable. Plus, its ability to support modifications makes it somewhat superior to a hard IP core. Moreover, the vendor would fully test the core and publish any known errors or limitations in its documentation.
A firm core does have some drawbacks. It offers limited portability compared to a soft IP core. Also, modifications to the source code are not possible, and it may cause some timing or performance issues when reused.
3. Soft IP core
A soft core is the most flexible type of IP core since it can be customized to map to any process technology and reused for a wide range of applications. It can exist as a modifiable netlist, which is a list of the logic gates and associated interconnections making up the IC. It can also be provided as Register Transfer Language code.
With a soft IP core, the licensee gets the source code with the license. This enables it to modify the IP to suit its application and easily integrate it with its modules. It can also reuse the core for many types of FPGAs.
One of the main drawbacks of a soft IP core is its cost. Since the vendor provides the modifiable source code, the soft core tends to be more expensive than a hard or firm core. In addition, the buyer/licensee may need to acquire individual IP core licenses. It may also have to put in extra effort customizing its applications. In addition, the application's performance may vary and not match its requirements.