Ride through racetrack memory and its storage implications

Why electric current and nanowires

Stuart Parkin, experimental physicist with IBM, proposed the concept of racetrack memory in 2002. In early 2008, a team of IBM scientists demonstrated the first racetrack memory device. Since then, IBM and other research teams have built upon and improved the technology. They have made it a more viable contender in the race toward an offering that can address the shortcomings of today's storage and memory systems.

HDDs, for example, rely on moving parts, which limit read/write speeds, increase the risk of mechanical failure, consume lots of power, generate excess heat and are noisy. On the other hand, SSDs cost more and suffer from endurance issues. Racetrack memory, though, is non-volatile, has zero standby leakage, and offers strong endurance and performance, in addition to its lower power consumption.

Racetrack memory incorporates spintronic memory-storage technology to deliver an entirely solid-state device with no moving parts. According to Parkin and See-Hun Yang at IBM Research, the operation of a spintronic device, such as racetrack memory, is based on the creation and manipulation of spin-polarized currents. Spintronics already creates extremely sensitive detectors of small magnetic fields capable of operating at room temperature and above, according to the researchers.

With racetrack memory, data is stored in an array of magnetic nanowires -- the racetracks -- that work together to provide a single memory system. Electrical currents push the data along the nanowires and past the access ports, which serve as interfaces to read/write data. That approach contrasts with HDDs, which move the read/write head across the spinning disks, rather than moving the data to the heads.

The spintronics technology that drives racetrack memory uses the spin and orientation of electron particles within the magnetic nanowires to represent the stored data. In this environment, the electrons point either up or down. This positioning and other quantum properties provide a system for mapping to the binary 1s and 0s that make up the data. When an electrical current is applied to the nanowire in a controlled manner, data bits can shift to the access port location to facilitate read/write operations.

Research teams are generally taking one of two approaches to moving the data bits within the nanowires. The first approach creates magnetic domains -- regions of opposing spin orientation where data can be encoded -- which are separated by domain walls only a few nanometers wide. The domain walls can shift to different places in the nanowire through current, so they deliver the data bits directly to the access ports.

The other method is based on magnetic skyrmions, which are tiny quasi-particle swirls that can be precisely controlled by applying current. Skyrmions are small and stable structures that can move at high speeds through the magnetic nanowire. They can also be quickly created and erased through electric pulses. Like data walls, the interaction between skyrmions plays an important role in storing and delivering data. However, skyrmions are smaller than data walls, so they can store more information within each nanowire.

If racetrack memory can live up to its hype, it could potentially replace both storage and memory devices.

How will enterprises use racetrack memory?

If racetrack memory can live up to its hype, it could potentially replace both storage and memory devices. Depending on the device type, racetrack memory promises to offer comparable or better performance, endurance and density and reduce energy consumption and costs. Those factors will play an increasingly important role in supporting big data, AI, telecommunications and the growing capabilities of hand-held devices.

Racetrack memory could prove especially beneficial to data storage that currently relies on HDDs, which are starting to reach their practical limitations in performance and capacity. Already, many organizations have turned to SSDs to support their mission-critical workloads. Racetrack memory outperforms HDDs by a significant margin, offers greater densities and requires less energy to support both read/write operations. The cost of racetrack memory is also expected to be on par with HDDs.

For many of the same reasons as HDDs, racetrack memory could also replace SSDs, including the latest 3D NAND devices and storage class memory (SCM) technology. For example, the read time for an Intel Optane SSD is around 10 microseconds. Although this is not nearly as fast as most subsystem memory, it is much better than the typical enterprise-class SSD and far exceeds the HDD. By comparison, racetrack memory promises speeds less than 250 nanoseconds, with some estimates coming in at less than 10 ns. In addition, racetrack memory should offer better endurance and higher densities than SSDs, along with lower costs and energy consumption.

Racetrack memory could replace subsystem memory, such as static RAM (SRAM) and DRAM, especially if it can achieve read/write times in the 10 ns range. This is especially true for DRAM, which is slower than SRAM. For example, the average read time for DRAM is about 30 ns, and the average write time is about 50 ns, speeds that racetrack memory should easily beat. Racetrack memory also consumes less energy than DRAM, is not as prone to leakage, supports greater densities and costs less.

Another important characteristic of racetrack memory is its non-volatility, unlike SRAM or DRAM, which makes it more versatile. For instance, enterprises could use racetrack memory for the computer's main memory but with the added ability to persist data, which could lead to improvements in application and OS performance and reliability. In addition, enterprises could use racetrack memory for system caches (L1, L2 or L3), the cache in GPUs, or any system or device that requires SRAM, DRAM or another type of RAM.

Potential pitfalls in developing racetrack memory

As promising as racetrack memory sounds, getting it from the experimental phase to the production phase is no small task. Researchers must better control data bit movement within the nanowires, an issue that can affect both performance and reliability. For example, racetrack memory based on domain walls currently lacks a mechanism to ensure that the domain walls shift correctly and align with the access ports. On the other hand, skyrmions can be more difficult to detect electrically than domain walls because of their smaller size.

Scientists are also working with materials at a nanoscale level, which leaves little room for deviation or error. Even the tiniest flaw in the nanowire can impact performance and reliability. For this reason, the material for the nanowire must meet precise specifications to ensure that it maximizes the spintronic benefits without destabilizing the internal structures. Skyrmions, for example, require specific material environments to maintain their stability. Even small thermal fluctuations can cause them to drift.

Indeed, there is still a lot that researchers don't yet know, such as how well racetrack memory will work as a replacement for high-capacity storage. In theory, the technology should be able to support significant densities, but there is no proof yet. Scientists have proposed extending their 2D designs to 3D storage devices, but it's not clear whether they can develop a device that will support data-intensive workloads and the massive data sets that drive them.

Whether racetrack memory is used for storage or memory, the device itself must deliver reliable read/write operations that can provide the necessary performance and ensure the reliable transfer of data. The nanoscale environment exacerbates that challenge. When the memory is based on data walls, for instance, the access ports must distinguish the domain spin orientations to carry out data bit encoding. For skyrmion-based memory, the access ports must detect a skyrmion's presence or absence.

Spintronics is still a relatively young field of research. There is still much to learn and understand about the quantum mechanics and the materials needed to optimize spintronics. In addition, the scientists -- along with other key players -- still need to design and develop the hardware and software necessary to connect the system's components together. They must also provide the necessary interface for working with other systems.

How close is racetrack memory to use?

Clearly, racetrack memory is a long way off before IT will see commercial devices that can plug into different systems. Although scientists have made significant progress in the last two decades, they must gain a better understanding of how the magnetic structures work and interact at the quantum level. The scientific community -- along with the supporting industry -- must also invest more resources into studying spintronics and the materials needed to build devices based on this technology.

Scientists still need to create comprehensive prototypes that span various uses and operate under multiple environmental conditions and with varying data loads. The prototypes must undergo extensive testing. A process must ensure the availability of production-ready materials, which means that scientists must first identify the best materials to use. Researchers must design and build the necessary hardware and software and properly prototype and test it all.

Given the challenges that still lie ahead, it will likely be longer than five years before racetrack memory is commercially viable, but it depends how researchers progress and the type of interest their work generates.

It also depends on other developments in memory. This includes advancements in existing technologies, such as NAND flash and SCM, and newer ones, such as phase-change RAM, ferro-electric RAM, 5D memory crystals and DNA storage. With so much data at stake, racetrack memory is only one contender among many that are vying for a piece of the data pie, so its future is as uncertain as the rest of the storage and memory industry.