RISC vs. CISC explained for data center systems

RISC vs. CISC processors

Today's x86 processor designs are an amalgamation of features and functionality from the last 30 years, right up to today's Intel-VT and AMD-V instructions to support hardware-assisted virtualization.

But there's a problem with this complex instruction set computing (CISC) approach; every new instruction or feature adds tens of thousands of transistors to the processor die, adding power demands and latency even if the instructions are rarely used. The chip is extremely versatile, but it runs hot and sucks power with ever-increasing clock speeds.

Processors run much more efficiently when tailored to a specific task. Reduced instruction set computing (RISC) strips out unneeded features and functionality, and builds on task-specific capabilities. Simpler, more reliable RISC processors provide the same effective computing throughput at a fraction of the power and cooling.

The question in CISC vs. RISC arguments is versatility vs. efficiency. Traditional x86 CISC processors can tackle almost any computing task using an extraordinarily comprehensive instruction set. This made CISC the preferred chip design for general-purpose computing platforms: enterprise servers, desktop PCs and laptop/notebook systems.

Purpose-built RISC processors sacrifice versatility for efficiency. Removing unneeded instructions dramatically reduces the processor's transistor count. Tackling fewer tasks in hardware means those tasks are performed faster, even at lower clock speeds (less power) than a full x86 CISC counterpart.

Printers, home routers, and even multifunction telephones and remote controls use RISC processors, and the concept is growing dramatically for fully featured computing platforms. A tablet or smartphone's RISC processor can deliver smooth video playback, fast webpage display and a responsive user interface for many hours on a battery charge, with no cooling devices. This same chip design paradigm is systematically finding traction in data center systems.

Examples of RISC processors

Chip designers, such as Intel, are forging ahead with RISC processors for data centers and endpoints. Intel's Atom processor family has diversified into numerous purpose-built variants using major parts, but not necessarily all, of the x86 instruction set.

The Atom single-core Silverthorne family for the mobile Internet device (MID) market supports MMX, SSE, SSE2, SSE3, SSSE3 and Enhanced SpeedStep Technology, but not all models support Hyper-Threading or Intel-VT. While an Atom-based system will support most basic x86 applications, it is not intended for virtualization in this case.

The Atom S12x9 family supports a complete system-on-a-chip (SoC) with 40 lanes of PCIe 2.0 for high I/O capacity. It is used in storage systems. The Atom Avoton is a 64-bit SoC processor that includes an Ethernet controller and is designed for microservers. The Atom Rangeley SoC processor is tailored for handling network traffic and used in entry- to mid-level routers, switches and security devices.

Linux-based multi-core SoC RISC processors like Tilera TILE Gx-8072 provide 72 interconnected RISC cores in the same package. You'll find these in low-power servers, allowing huge complements of processor cores for tasks like network data handling and video transcoding.

A more general expression of RISC processors is the ARMv8 reference design licensed by Advanced RISC Machines (ARM). Tablet processors like Apple's A6 and NVIDIA's Tegra 3 are based on ARM's Cortex A9 RISC processor. The 64-bit Cortex-A57 design supports applications programmed in Linux, Linaro and other open-source languages. AMD will develop a RISC SoC processor for enterprise servers based on the Cortex-A57 design.