Explore the evolution of Intel and AMD server processors

Intel's evolving data center strategy

Earlier this year, Intel released its third-generation Xeon Scalable processor, Ice Lake. The chip is based on the Sunny Cove microarchitecture that Intel first used to update its 10th-generation client processors. The device is built on Intel's 10nm+ process, which is the second generation of its 10nm process.

The chip includes at least 28 cores with an approximately 18% increase in instructions per clock (IPC) over the Skylake architecture used in previous-generation Xeon Scalable products.

According to Intel, there are several significant improvements in the Sunny Cove microarchitecture, including:

• new system-on-chip architecture with three independently clocked Ultra Path Interconnect links for multiprocessor connections;
• an improved, higher capacity instruction front-end and branch predictor;
• wider and deeper allocation queues and execution resources;
• enhancements in translation lookaside buffers (TLBs), which reduce the latency of accessing memory;
• larger mid-level cache (L2) plus a second fixed multiply-add to accelerate vector operations;
• instructions to accelerate cryptography and compression/decompression operations;
• new I/O virtualization design with up to three times the bandwidth for large payloads and integrated PCIe Gen 4 controllers;
• support for Total Memory Encryption of physical RAM; and
• better performance and lower latency when switching between power management states.

At Architecture Day 2020, Intel said the next-generation Xeon processor code-named Sapphire Rapids will support DDR5; PCIe Gen 5; Compute Express Link 1.1; advanced matrix extensions to accelerate AI calculations; and a data streaming accelerator to optimize streaming data movement and transformation.

Intel in June said it expects Sapphire Rapids to be in production in the first quarter of 2022. Expect more technical information from the vendor at Hot Chips 2021 in August and Intel Innovation in October.

AMD not slowing down

AMD keeps clicking with new client, server and GPU products that promise to widen its price-performance lead via third-generation Zen 3 cores in its Epyc server processors.

Unlike Intel, AMD skipped the 10nm process node. The company has been fabricating its chips on a 7nm TSMC process and uses an updated version for Zen 3.

Zen 3 features several architectural improvements, including:

• better branch prediction via a larger L1 cache, faster recovery from missed predictions and algorithmic improvements;
• faster execution engine through larger execution windows, lower latency, wider integer execution units, faster multiply-accumulate and other changes; and
• higher load-store bandwidth, more flexibility in load-store operations and improvements to the TLBs.

However, the biggest change with Zen 3 is the chiplet topology, in which each 8-core chiplet is organized around a single 32 MB L3 cache rather than being partitioned into two 4-core/16 MB-cache complexes. The design doubles the L3 space available to each core, increasing the hit rate, and reduces effective memory latency between any two cores. Collectively, the improvements mean that Zen 3 delivers a 19% improvement in IPC and 24% more performance per watt, as compared to Zen 2.

Zen 3 products use the same chiplet packaging as existing Epyc models with eight 8-core processor chips surrounding an I/O-memory module.

AMD's roadmap suggests the Zen 4 Genoa processors, using a new 5nm process, will arrive in 2022.